1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to light emitting devices and methods of fabricating light emitting devices.
2. Description of Related Art
Light emitting diodes and laser diodes are well known solid state electronic devices capable of generating light upon application of a sufficient voltage. Light emitting diodes and laser diodes may be generally referred to as light emitting devices (LEDs). Light emitting devices typically include a p-n junction formed in an epitaxial (epi) layer such as gallium nitride (GaN). The epi layer is usually grown on a substrate such as sapphire (Al2O3), silicon (Si), silicon carbide (SiC), or gallium arsenide (GaAs). The wavelength distribution of the light generated by the LED depends on the material from which the p-n junction is fabricated and the structure of the thin epitaxial layers that include the active region of the device. Commercial high-efficiency LEDs are typically fabricated from two classes of III-V semiconductor materials. Group-III nitride (III-N) based materials are used for the ultraviolet to blue-green color range, and Group-III arsenide-phosphide (III-AsP) for yellow to near-infrared.
There has been a great deal of recent interest in LEDs formed of Group-III nitride based material systems because of their unique combination of material characteristics, including high breakdown fields, wide bandgaps (3.36 eV for GaN at room temperature), large conduction band offset, and high saturated electron drift velocity. The doped and active layers in such devices are typically formed on a substrate which can be made from a variety of different materials such as silicon (Si), silicon carbide (SiC), and sapphire (Al2O3). SiC wafers are often preferred for such heterostructures because they have a much closer crystal lattice match to Group-III nitrides, resulting in Group-III nitride films of higher quality. SiC also has a very high thermal conductivity, such that the total output power of Group-III nitride devices on SiC is not limited by the thermal resistance of the wafer, as is the case for many devices formed on sapphire or Si. The availability of semi-insulating SiC wafers also provides the capacity for device isolation and reduced parasitic capacitance, which makes commercial devices possible.
During fabrication of semiconductor devices or circuits such as chips and multichip modules (MCM), a substrate (substrate wafer, growth wafer) provides the base or support for subsequent processing operations in which additional layers, components, or other materials are applied (e.g. epitaxial materials or layers, printed circuit boards, and disk platters). Patterning is a fabrication process in which a specific design can be introduced into a layer or surface during semiconductor fabrication. Patterning can be achieved in a number of ways, such as selectively depositing or selectively removing a material. Wet etching (chemical etching, chemical milling) is a patterning process used in semiconductor fabrication that removes a material by relying on chemical reactions in the liquid phase. The process typically uses acids, bases or other chemicals to dissolve away unwanted materials. Based on the nature, etching is broadly classified into isotropic and anisotropic. Isotropic etching is same in all directions while anistropic etching is direction sensitive. Material to be etched and type of the etchant determines the nature of the etch i.e. isotropic or anisotropic. For example, silicon is etched anisotropically in potassium hydroxide (KOH) while most of the commonly used metals (e.g. Au, Ag, Ni, Sn) and dielectrics (e.g. SiO2, SiN) in semiconductor technology utilize isotropic etchants. Anisotropic etch provides better control over the patterns or shapes to be produced while isotropic etch is employed in blanket etching or with combination of different materials for selective etching (patterning).
Selective wet etch processes rely on the different etch rates of an etchant for different materials. In a typical selective wet etch process, one material is etched rapidly while another is etched very slowly or not etched at all. An aqueous HF solution, for example, can etch SiO2 very rapidly while not etching silicon. For any particular etchant, the etch rate for the film being etched should be higher than the etching rates for both the mask and/or the substrate. Due to resolution limitations inherent in wet etching processing, the technique is generally used to pattern coarse features such as bond pads or large vias where, for example, an aspect ratio of 1 to 5 can be achieved reliably. However, despite such limitations, wet etch processing has found widespread use because it provides many advantages including low cost, high reliability, high throughput, and excellent selectivity with respect to both mask and substrate materials.
A typical wet etch process involves coating the target or etch layer on the semiconductor wafer with a etch mask. One of the most commonly used etch mask is photoresist. Standard Photolithography is performed in the photoresist to expose the regions of the target layer to be etched. Wafer is immersed in the etchant to etch the target layer. After etching, the mask layer, in this case photoresist is usually then removed, leaving one or more patterned target layers which may require further processing in order to cure, clean, or remove residual solvent. Most materials are patterned in this manner, including silicon dioxide (SiO2), Au and Sn.
Modern device architectures can require patterning of a composite gold-tin (AuSn) solder material during fabrication. Individually, gold (Au) or tin (Sn) metal films can be wet etched quite readily after deposition and commercial etches suitable for such processes are available and well known. The chemistries of the two metals, however, are quite different, such that no single chemical will etch both metals together. Therefore, patterning of composite AuSn solder material during device fabrication is typically achieved during deposition by using a selective area deposition technique, rather than by post-deposition selective etching of a blanket AuSn layer.
Selective deposition techniques typically used to pattern AuSn solder materials can include screen-printing through a patterned foil, electro-plating or vacuum deposition using a patternable sacrificial layer such as photo-resist, and physical cutting of free-standing thick films to create preforms or other materials molded into predetermined shapes, volumes, or dimensions, including without limitation a solder preform. These technologies, however, suffer from certain disadvantages.
Due to incorporation of flux in the solder paste, screen-printing of solder paste is not a clean process. The paste typically undergoes reflow to drive off the flux, which can lead to contamination and leave voids in the material. Minimum thickness and dimension requirements are therefore generally large for layers formed in this manner, typically in the range of 20-50 microns. Preforms can be used for selective solder bumping. However, the technology is thickness and size-limited, and also costly due to the need to physically place preform on a wafer.
In practice, therefore, the use of selective area deposition restricts the range of device architectures that are possible for AuSn solder due to the inherent limitations of available deposition techniques. Additionally, in some cases it is simply not desirable to pattern the AuSn at the time it is deposited. A uniform bond interface is simpler and preferred over a patterned bond, for example, when AuSn is used to wafer-bond two substrates.